1. Field of the Invention
The present invention relates to a method of fabricating semiconductor devices, and more particularly to a method of fabricating a MOS transistor using a total gate silicidation process.
2. Description of the Related Art
MOS transistors are widely in use as discrete switching devices in semiconductor devices. With the increase in integration of semiconductor devices, the size of the MOS transistor has been reduced. As a result, the reduction in the channel length of the MOS-transistor causes a short channel effect.
The junction depth of the source/drain region of the MOS transistor is required to be reduced to improve the short channel effect. The reduction of the junction depth of the source/drain region increases the sheet resistance of the source/drain region, which results in a decreased ability to provide an appropriate driving current required in a high performance transistor. Therefore, a self-aligned silicide process is widely used in order to decrease the sheet resistance of the source/drain region, and to reduce the sheet resistance of the gate electrode.
The self-aligned silicide process has been developed and widely used to form a silicide layer at the source/drain region and on top of the polysilicon of the gate region at the same time. In accordance with this process, the thickness of the silicide layer formed at the source/drain region should be smaller than the junction depth.
Also, with the MOS transistor scaled down, the thickness (Tox) of the gate insulating layer has been reduced to avoid the short channel effect and improve the current drivability. The reduction of the thickness of the gate insulating layer increases the capacitance of the gate insulating layer so as to improve the current drivability.
However, as a result of the reduction of the thickness of the gate insulating layer, poly depletion occurs in the MOS transistor, in which a polysilicon layer is used as a gate electrode. The poly depletion layer increases the electrical equivalent thickness of the gate insulating layer, and decreases the drive current.
As a method of solving the poly depletion problem, use of a metal gate has been widely studied. However, the metal gate has a drawback in the form of a difficulty in controlling threshold voltage of a transistor. Specifically, the threshold voltages of the NMOS transistor region and the PMOS transistor region should be controlled in order to employ the metal gate in a CMOS transistor. However, the use of a different metal gate in each MOS transistor makes the fabrication processes too complicated to be practicably employed.
One method for solving the problems of poly depletion and the metal gate is taught by Tavel et. al. in a research paper entitled, “Totally Silicided (CoSi2) Polysilicon: a novel approach to very low-resistive gate (˜2Ω/□) without metal CMP nor etching,” (IEDM 2001, p.825–828, December of 2001).
However, the method disclosed in the above paper also has a drawback in that a threshold voltage (Vth) is increased due to a decrease of the absolute value of a flat band voltage (Vfb) since a midgap material is used as a metal gate, and that the fabrication processes are complicated since the silicide layer of the source/drain region and the gate silicide layer are formed respectively using separate processes. Specifically, in order to form the silicide layer of the source/drain region and the gate silicide layer using separate proecsses, a chemical mechanical polishing process (CMP) is required.
In order to concurrently form the silicide layer of the source/drain region and the gate silicide layer using the total gate silicide process, it is necessary to reduce the gate height. However, when the gate height is even slightly reduced, ions are injected into a channel region during the ion implantation process into the source/drain regions, which causes a problem that leakage current of the MOS transistor is increased.
As a result, it is necessary to optimize the fabrication method of the MOS transistor being capable of solving the poly depletion problem.